Semiconductor device and its manufacturing method

ABSTRACT

A stacked type semiconductor device, complying with reductions in a mounting height and a mounting area and weight thereof, is realized with high-performance and at low cost using an existing production line. A non-lead type semiconductor device is provided which comprises: a sealing body made of an insulative resin; a tab on which a semiconductor chip is mounted; a plurality of leads each having one surface exposed on a mounting surface of the sealing body; a first semiconductor chip located in the sealing body and having a first surface to be a circuit forming surface and a second surface opposite to the first surface, the second surface being supported on one surface of the tab through adhesive; a plurality of electrode pads formed in the periphery of the first surface of the first semiconductor chip; conductive wires for electrically connecting the electrode pads and the leads; a second semiconductor chip having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and stacked and mounted on the first surface of the first semiconductor chip toward the second surface thereof; a plurality of electrode pads formed on the first surface of the second semiconductor chip; and conductive wires for electrically connecting the electrode pads of the second semiconductor chip and the leads.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a manufacturing technique of a resin-sealed semiconductor device, and particularly to a technique effectively applied to a semiconductor device suitable for high-density mounting like a multi-chip package in which a plurality of LSI chips are embedded in one package.

[0002] With demands for the size reduction of a semiconductor package in recent years, there has been demanded a semiconductor device, which is generally called a multi-chip package (hereinafter “MCP”) or system-in package in which a plurality of LSI chips are embedded in one package. As an example of such an MCP structure, there is known a stacked structure in which two LSI chips are, for example, stacked and resin-molded to form a package. As a concrete example of the MCP with the stacked structure, an MCP of a QFP (Quad Flat leaded Package) type in which LSI chips are stacked in the package is disclosed in the gazette of Japanese Patent Laid-Open No. 2001-267488 etc. The MCP of this type includes: a plurality of LSI chips stacked; a plurality of wires to electrically connect electrode pads of the LSI chips and external connection leads; a resin sealing body formed by resin-mold a plurality of inner leads; and outer leads led out from the side surfaces of the resin sealing body. This is mounted to a mounting board by these outer leads. Also, as another example of the MCP, there is known the MCP of a so-called CSP (Chip Size Package) type, as described in the gazette of Japanese Patent Laid-Open No. 11-204720, in which a plurality of LSI chips are stacked on a wiring board made of epoxy or polyimide and electrode pads of the respective LSI chips and electrodes on the wiring board are electrically connected by wire bonding or face-down bonding and the respective LSI chips on the wiring board and the electrically connected portions thereof are molded in resin.

SUMMARY OF THE INVENTION

[0003] Since the outer leads are led out from the side surfaces of the resin sealing body and the resin sealing bodies are structurally located on and below a tab, the MCP of the above-mentioned QFP type inevitably become large in a mounting area and a mounting height, thereby being unsuitable for the mounting onto the mounting board built in a current mobile device such as a cellular phone or a mobile computer. Also, with respect to the MCP of the CSP type, since the mounting area thereof is small, it is suitable to the mounting onto the mounting board of the mobile device. Thus, the CSP type is advantageous when the package is rather multifunctional and the number of external connection pins is large, but since an insulative board (resin board or film made of epoxy, polyimide, etc.), ball-shaped mounting external terminals made of solder, and the like are used as components, the material cost is high and a special manufacturing machine is required and the number of steps is increased. Consequently, when the number of external connection pins is small, there arises a problem such that the CSP type becomes relatively expensive. Additionally, since the ball-shaped mounting external terminals are used, its height inevitably becomes increased and there are limits to a reduction in the mounting height. Furthermore, since there are restrictions in the chip size and the arrangement of the electrode pads in stacking the LSI chips, it is difficult to use the existing LSI chips and connect respective electrode pads between the two LSI chips stacked. Therefore, a problem occurs such that the extension of the leads is restricted.

[0004] The inventors of the present invention have conducted the intense examination to effectively solve the above-mentioned problems. Thus, an object of the present invention is to provide a multi-chip type semiconductor device, which is very small in the mounting area and the mounting height and can be manufactured at low cost with using the existing production line, and to provide its manufacturing method.

[0005] The above and other problems, objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006] The typical ones of the inventions disclosed in this application will be briefly described as follows.

[0007] (1) An aspect of the present invention is a semiconductor device, which comprises: a sealing body made of an insulative resin; a tab on which a semiconductor chip is mounted; a plurality of leads each having one surface exposed on a mounting surface of said sealing body; a first semiconductor chip located in said sealing body and having a first surface to be a circuit forming surface and a second surface opposite to the first surface, the second surface being supported on one surface of said tab through adhesive; a plurality of electrode pads formed in the periphery of the first surface of said first semiconductor chip; conductive wires for electrically connecting said electrode pads and said leads; a second semiconductor chip having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and stacked and mounted on the first surface of the first semiconductor chip toward the second surface thereof; a plurality of electrode pads formed on the first surface of said second semiconductor chip; and conductive wires for electrically connecting the electrode pads of said second semiconductor chip and said leads.

[0008] Said second semiconductor chip is arranged at a position inside the electrodes of said first semiconductor chip. Bumps are formed on the electrode pads of said second semiconductor chip, one end of each of said wires is connected to each of said leads or the electrode pads of said first semiconductor chip, and the other end thereof is connected through each of said bumps. At least one of the plurality of electrode pads of said first semiconductor chip are electrically connected to said tab by said wires.

[0009] (2) Another aspect of the present invention is a semiconductor device, which comprises: a sealing body made of an insulative resin; a tab for supporting a semiconductor chip; a plurality of leads each having one surface exposed on a mounting surface of said sealing body; a first semiconductor chip located in said sealing body, having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and supported on one surface of said tab through adhesive; a plurality of electrode pads formed in the periphery of the first surface of said first semiconductor chip; conductive wires for electrically connecting said electrode pads and said leads; a second semiconductor chip having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and stacked and mounted on the first surface of the first semiconductor chip; and conductive wires for electrically connecting a plurality of electrode pads formed on the first surface of said second semiconductor chip and said leads.

[0010] Said tab is formed into a frame shape; the first semiconductor chip is adhered to one surface of the frame-shaped tab at a position inside the electrode pads on the first surface thereof; said second semiconductor chip is located on the first surface of said first semiconductor chip and at a position inside an opening of said frame-shaped tab; and said frame-shaped tab and said second semiconductor chip are adhered on the same surface. Said first semiconductor chip and said second semiconductor chip are connected to each other by connecting at least two of the electrode pads formed on each first surface through said conductive wires, or connected to said frame-shaped tab through said conductive wires.

[0011] (3) Another aspect of the present invention is a semiconductor device, which comprises: a sealing body made of an insulative resin; a tab for supporting a semiconductor chip; a plurality of leads each having one surface exposed on a mounting surface of said sealing body; a first semiconductor chip located in said sealing body, having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and supported on one surface of said tab through adhesive; a plurality of electrode pads formed in the periphery of the first surface of said first semiconductor chip; and conductive wires to electrically connect said electrode pads and said leads, wherein the device includes a second semiconductor chip having a first surface to be a circuit forming surface and a second surface opposite to the first surface; the second surface of said second semiconductor chip is adhered to one surface of said tab; said electrode pads and said leads and a plurality of electrode pads formed on the first surface of said second semiconductor chip are electrically connected through the conductive wires; the first surface of said first semiconductor chip is adhered to the other surface of said tab; and said tab and said second semiconductor chip are each located at a position inside the electrode pads on the first surface of the first semiconductor chip.

[0012] Said first semiconductor chip and said second semiconductor chip are connected to each other by connecting at least two of the electrode pads formed on each first surface through said conductive wires, or connected to said tab through said conductive wires.

[0013] (4) Still another aspect of the present invention is a manufacturing method for a semiconductor device, comprising the steps of:

[0014] (a) preparing a lead frame having a first frame portion, a second frame portion formed inside said first frame portion, a plurality of device regions formed inside said second frame portion, and tabs and a plurality of lead portions, which are formed in each of said plurality of device regions;

[0015] (b) supporting a plurality of first semiconductor chips, each of which has a plurality of electrode pads, on the respective tabs on the plurality of device regions of said lead frame;

[0016] (c) supporting a plurality of second semiconductor chips, each of which has a plurality of electrode pads, on a first surface to be a circuit forming surface of each of said plurality of first semiconductor chips;

[0017] (d) electrically connecting each plurality of electrode pads of said first semiconductor chips and said second semiconductor chips to a plurality of lead portions of said lead frame through a plurality of wires, respectively;

[0018] (e) forming a resin sealing body such that said first and second semiconductor chips, said wires, and portions of said leads are sealed and the portions of said leads are exposed from the mounting surface; and

[0019] (f) after the step of forming said resin sealing body, separating said lead frame and said resin sealing body per each of said device regions.

[0020] (5) Still another aspect of the present invention is a manufacturing method for a semiconductor device, in which a plurality of tabs each formed into a flat shape are used and a plurality of first and second semiconductor chips are supported on and below each of them, comprising the steps of:

[0021] (a) preparing a lead frame having a first frame portion, a second frame portion formed inside said first frame portion, a plurality of device regions formed inside said second frame portion, and tabs and a plurality of lead portions, which are formed in each of said device regions;

[0022] (b) adhering a first surface to be each circuit forming surfaces of a plurality of first semiconductor chips each having a plurality of electrode pads and one surface of each of said tabs, to the plurality of device regions of said lead frame, through an insulative adhesive;

[0023] (c) supporting a plurality of second semiconductor chips, each having a plurality of electrode pads, onto one surfaces of said plurality of tabs, through conductive adhesive;

[0024] (d) electrically connecting the plurality of electrode pads of each of the plurality of first semiconductor chips and second semiconductor chips to the plurality of lead portions of said lead frame through a plurality of wires, respectively;

[0025] (e) forming a resin sealing body such that said plurality of first and second semiconductor chips, the plurality of wires, and portions of said plurality of leads are sealed and the portions of said plurality of leads are exposed from the mounting surface; and

[0026] (f) after the step of forming said resin sealing body, separating said lead frame and resin sealing body per each of said device regions.

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0027]FIG. 1 is a cross-sectional view showing an example of a structure of a semiconductor device according to a first embodiment of the present invention.

[0028]FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. 1.

[0029]FIG. 3 is a bottom plan view (mounting surface) showing the structure of the semiconductor device shown in FIG. 1.

[0030]FIG. 4 is a plan view showing an example of a structure of a lead frame used in assembling the semiconductor device shown in FIG. 1.

[0031]FIG. 5 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 4.

[0032]FIG. 6 is a cross-sectional view showing an example of the structure obtained after the die bonding of a first semiconductor chip in assembling the semiconductor device shown in FIG. 1.

[0033]FIG. 7 is a cross-sectional view showing an example of the structure obtained after the die bonding of a second semiconductor chip in assembling the semiconductor device shown in FIG. 1.

[0034]FIG. 8 is a cross-sectional view showing an example of the structure obtained after the wire bonding in assembling the semiconductor device shown in FIG. 1.

[0035]FIG. 9 is a cross-sectional view showing an example of the structure of a molding state obtained in assembling the semiconductor device shown in FIG. 1.

[0036]FIG. 10 is a cross-sectional view showing an example of the structure of an outer-packaging plated state obtained in assembling the semiconductor device shown in FIG. 1.

[0037]FIG. 11 is a cross-sectional view showing an example of the structure of a dicing state obtained in assembling the semiconductor device shown in FIG. 1.

[0038]FIG. 12 is a cross-sectional view showing an example of the structure obtained after the dicing in assembling the semiconductor device shown in FIG. 1.

[0039]FIG. 13 is a cross-sectional view showing an example of the structure obtained after the mounting onto a board in mounting the semiconductor device shown in FIG. 1.

[0040]FIG. 14 is a cross-sectional view showing an example of a structure of a semiconductor device according to a second embodiment of the present invention.

[0041]FIG. 15 is a plan view showing the structure of the semiconductor device shown in FIG. 14.

[0042]FIG. 16 is a bottom plan view (mounting surface) showing the structure of the semiconductor device shown in FIG. 14.

[0043]FIG. 17 is a plan view showing an example of a structure of a lead frame used in assembling the semiconductor device shown in FIG. 14.

[0044]FIG. 18 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 17.

[0045]FIG. 19 is a cross-sectional view showing an example of the structure obtained after the die bonding of a first semiconductor chip in assembling the semiconductor device shown in FIG. 14.

[0046]FIG. 20 is a cross-sectional view showing an example of the structure obtained after the die bonding of a second semiconductor chip in assembling the semiconductor device shown in FIG. 14.

[0047]FIG. 21 is a cross-sectional view showing an example of the structure obtained after the wire bonding in assembling the semiconductor device shown in FIG. 14.

[0048]FIG. 22 is a cross-sectional view showing an example of the structure of a molding state obtained in assembling the semiconductor device shown in FIG. 14.

[0049]FIG. 23 is a cross-sectional view showing an example of the structure of a outer-packaging plated state obtained in assembling the semiconductor device shown in FIG. 14.

[0050]FIG. 24 is a cross-sectional view showing an example of the structure of a lead-cut state obtained in assembling the semiconductor device shown in FIG. 14.

[0051]FIG. 25 is a cross-sectional view showing an example of the structure obtained after cutting the leads in assembling the semiconductor device shown in FIG. 14.

[0052]FIG. 26 is a cross-sectional view showing an example of the structure obtained after the mounting onto a board in mounting the semiconductor device shown in FIG. 14.

[0053]FIG. 27 is a cross-sectional view showing an example of a structure of a semiconductor device according to a third embodiment of the present invention.

[0054]FIG. 28 is a plan view showing the structure of the semiconductor device according to the third embodiment shown in FIG. 27.

[0055]FIG. 29 is a cross-sectional view showing a modified example in the third embodiment.

[0056]FIG. 30 is a bottom plan view (mounting surface) showing the structure of the semiconductor device shown in FIG. 29.

[0057]FIG. 31 is a cross-sectional view showing an example of a structure of a semiconductor device according to a fourth embodiment of the present invention.

[0058]FIG. 32 is a plan view showing the structure of the semiconductor device according to the fourth embodiment shown in FIG. 31.

[0059]FIG. 33 is a cross-sectional view showing a modified example in the fourth embodiment shown in FIG. 31.

[0060]FIG. 34 is a plan view of a semiconductor device showing the case where a microcomputer is stacked on a first semiconductor chip 2 and an SRAM is stacked on the second semiconductor chip 3 in the semiconductor device.

[0061]FIG. 35 shows an example of the semiconductor device in which external connection terminals are arranged on two sides, and is a plan view of a semiconductor device showing the case where a flash microcomputer is stacked on the first semiconductor chip 2 and a DRAM is stacked on the second semiconductor chip 3.

[0062]FIG. 36 is a plan view of a semiconductor device showing the case where a flash microcomputer is stacked on the first semiconductor chip 2 and a DRAM is stacked on the second semiconductor chip 3 in the semiconductor device.

[0063]FIG. 37 is plan view of a semiconductor device showing the case where a microcomputer is stacked on the first semiconductor chip 2 and two SRAMs are respectively stacked on the second and third semiconductor chips in the semiconductor device.

[0064]FIG. 38 is a cross-sectional view showing the state where the semiconductor device is mounted on a multi chip module.

[0065]FIG. 39 is a plan view showing the state where the semiconductor device is mounted on the multi chip module.

[0066]FIG. 40 is a cross-sectional view showing an example of a structure of a conventional semiconductor device.

[0067]FIG. 41 is a plan view showing the structure of the semiconductor device shown in FIG. 40.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

[0068] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

[0069] (First Embodiment)

[0070]FIG. 1 is a cross-sectional view showing an example of a structure of a semiconductor device according to a first embodiment of the present invention; FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. 1; FIG. 3 is a bottom plan view (mounting surface) showing the structure of the semiconductor device shown in FIG. 1; FIG. 4 is a plan view showing an example of a structure of a lead frame used in assembling the semiconductor device shown in FIG. 1; FIG. 5 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 4; FIG. 6 is a cross-sectional view showing an example of the structure obtained after the die bonding of a first semiconductor chip in assembling the semiconductor device shown in FIG. 1; FIG. 7 is a cross-sectional view showing an example of the structure obtained after the die bonding of a second semiconductor chip in assembling the semiconductor device shown in FIG. 1; FIG. 8 is a cross-sectional view showing an example of the structure obtained after the wire bonding in assembling the semiconductor device shown in FIG. 1; FIG. 9 is a cross-sectional view showing an example of the structure of a molding state obtained in assembling the semiconductor device shown in FIG. 1; FIG. 10 is a cross-sectional view showing an example of the structure of an outer-packaging plated state obtained in assembling the semiconductor device shown in FIG. 1; FIG. 11 is a cross-sectional view showing an example of the structure of a dicing state obtained in assembling the semiconductor device shown in FIG. 1; FIG. 12 is a cross-sectional view showing an example of the structure obtained after the dicing in assembling the semiconductor device shown in FIG. 1; and FIG. 13 is a cross-sectional view showing an example of the structure obtained after the mounting onto a board in mounting the semiconductor device shown in FIG. 1.

[0071] A semiconductor device shown in FIGS. 1 to 3 is a semiconductor package of a resin-sealed type and a surface-mounting type employing a lead frame. In the description of the first embodiment, the tab-exposed type semiconductor device 6 is taken as an example of this semiconductor device.

[0072] As shown in FIG. 1, in the semiconductor device 6, a first semiconductor chip 2 is adhered and supported on a second surface opposite to a first surface to be a circuit forming surface, via a conductive die bond material 8 a such as silver paste or adhering film on a tab 1 e (chip mounting portion). A second surface of a second semiconductor chip 3 is stacked and mounted on the first surface of the first semiconductor chip via an insulative die bond material 8 b such as silicone rubber and insulative sheet, etc. Also, a plurality of electrode pads 2 a and 3 a of the respective semiconductor chips and a plurality of leads 1 a are connected by conductive wires 5 such as gold wires.

[0073] At this time, since the electrode pads in the periphery of the second semiconductor chip 3 are located inside the electrode pads in the periphery of the first semiconductor chip 2, it is easily possible to connect the plurality of electrode pads 2 a and 3 a of the respective semiconductor chips and the plurality of leads 1 a through the conductive wires 5.

[0074] Bumps 3 b made of gold or the like are formed on the plurality of electrode pads 3 a of the second semiconductor chip 3 in advance in the same manner as that used to form wire bumps. In performing the wire bonding, the side of each lead 1 a or the first semiconductor chip 2 is first bonded by using gold balls (tips) formed on the wires 5 (hereinafter “first bonding”). Thereafter, the tails (end) of the wires 5 are bonded to the bumps 3 b (hereinafter “second bonding”), whereby each angle of the wires 5 on the bumps 3 b becomes almost horizontal. Therefore, it is possible to keep lower the height of the wires and achieve the reduction of thickness of the semiconductor device 6 even when the semiconductor chips are stacked.

[0075] The side of the electrode pad 2 a on the first semiconductor chip 2 is connected by the first bonding and the side of each lead 1 a is connected by the second bonding. Further, the first semiconductor chip 2 and the tab 1 e are also wire-bonded. Accordingly, this device is one with a tab-exposed structure in which the tab 1 e and tab suspension leads 1 g are exposed from the mounting surface 4 a.

[0076] The resin used to form a sealing resin portion 4 is, for example, thermosetting epoxy resin etc.

[0077] Note that the semiconductor device 6 is assembled through a method (package molding) such that a plurality of device regions are sealed in one sealing resin body and the semiconductor-sealing resin portion is cut and divided into each of the device regions by the dicing.

[0078] Next, the manufacturing method for the semiconductor device 6 according to the first embodiment will be described.

[0079] First, a lead frame 1 as shown in FIG. 4 is prepared, which includes: an outer frame portion 1 h to be a first frame portion; an inner frame portion 1 j to be a second frame portion formed inside the outer frame 1 h; a plurality of device regions 1 k to be device regions formed inside the inner frame portion 1 j; a plurality of leads 1 a to be electrode portions formed in each of the plurality of device regions 1 k; and a plurality of tabs 1 e to be chip mounting portions formed in each of the plurality of device regions 1 k.

[0080] Next, as shown in FIG. 6, a plurality of first semiconductor chips 2, each having a plurality of electrode pads 2 a, are adhered and supported, on the second surface opposite to the first surface to be a circuit forming surface, via a conductive die bond material 8 a such as silver paste or adhering film, the second surface being over the respective tabs 1 e of the plurality of device regions 1 k of the lead frame 1 (die bonding).

[0081] Subsequently, as shown in FIG. 7, the second surface of the second semiconductor chip 3, which is opposite to the first surface to be a circuit forming surface, is adhered and supported on the first surface of the first semiconductor chip 2 via the insulative die bond material 8 b such as silicone rubber or insulative sheet, etc.

[0082] Next, as shown in FIG. 8, through conductive wires 5 such as gold wires etc., the plurality of electrode pads 2 a of the first semiconductor chip 2 are connected to the plurality of leads 1 a, the tab 1 e, or some of the electrode pads 3 a of the second semiconductor chip 3. Furthermore, the plurality of electrode pads 3 a of the second semiconductor chip 3 are connected to the plurality of leads 1 a or the tab 1 e (wire bonding). In this case, bumps made of gold etc. are formed on the electrode pads 3 a of the second semiconductor chip 3 in advance, for example, in the same manner as that used to form wire bumps. The wire bonding is used as the first bonding on the side of each lead 1 a or the first semiconductor chip 2, and as the second bonding on the side of each bump. The second bonding is performed to the bumps.

[0083] Subsequently, as shown in FIG. 9, the plurality of first semiconductor chips 2, the plurality of second semiconductor chips 3, the plurality of wires 5, and the parts of the leads 1 a and the tabs 1 e of the lead frame 1 are covered with a molding die 10, and the package molding is performed for filling a sealing resin into a cavity 10 c. By so doing, the sealing resin portion 4 is formed as shown in FIG. 10.

[0084] Note that, instead of the package molding in this case, a method of individually sealing the device regions by each cavity separated is of course available.

[0085] Thereafter, as shown in FIG. 10, a plating film 7 made of solder is formed by, for example, an electroplating method on the surface of the external connection terminal 1 b of each lead 1 a and the surface of the tab 1 e, which are exposed on the mounting surface 4 a of the sealing resin portion 4.

[0086] Then, by the dicing employing a dicing blade 9 shown in FIG. 11, the lead frame 1 and the sealing resin portion 4 are cut together per each of the device regions, thereby being individualized as shown in FIG. 12. Each sealing resin portion, which is formed per each of the device regions by the individual cavity, is individualized with a cutting blade.

[0087]FIG. 13 is an example showing a structure of the state where the semiconductor device 6 completed by individualization is mounted on the mounting board 11. Electrodes (lands) 11 a are provided on one surface of the mounting board 11 so as to correspond to the leads 1 b, the tab 1 e, and the tab suspension leads 1 g to be the external connection terminals of the above-mentioned semiconductor device 6. Thus, the leads 1 b, the tab 1 e, and the tab suspension leads 1 g to be the external connection terminals of the semiconductor device 6 are overlapped on these lands 11 a, and are electrically connected via a connection material 12 such as solder etc.

[0088] The first embodiment has, in view of the reliability, a structure in which the tab surface exists inside the package in order to enlarge the contact area between the tab surface and the resin for forming the package. Also, it has, in view of the heat radiation, a structure in which the tab is made larger than the chip and is exposed to the mounting surface side in order to transmit, to the wide area, heat generated in the semiconductor chip.

[0089] (Second Embodiment)

[0090]FIG. 14 is a cross-sectional view showing an example of a structure of a semiconductor device according to a second embodiment of the present invention; FIG. 15 is a plan view showing the structure of the semiconductor device shown in FIG. 14; FIG. 16 is a bottom plan view (mounting surface) showing the structure of the semiconductor device shown in FIG. 14; FIG. 17 is a plan view showing an example of a structure of a lead frame used in assembling the semiconductor device shown in FIG. 14; FIG. 18 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 17; FIG. 19 is a cross-sectional view showing an example of the structure obtained after the die bonding of the first semiconductor chip in assembling the semiconductor device shown in FIG. 14; FIG. 20 is a cross-sectional view showing an example of the structure obtained after the die bonding of a second semiconductor chip in assembling the semiconductor device shown in FIG. 14; FIG. 21 is a cross-sectional view showing an example of the structure obtained after the wire bonding in assembling the semiconductor device shown in FIG. 14; FIG. 22 is a cross-sectional view showing an example of the structure of a molding state obtained in assembling the semiconductor device shown in FIG. 14; FIG. 23 is a cross-sectional view showing an example of the structure of an outer-packaging plated state obtained in assembling the semiconductor device shown in FIG. 14; FIG. 24 is a cross-sectional view showing an example of the structure of a lead-cut state in assembling the semiconductor device shown in FIG. 14; FIG. 25 is a cross-sectional view showing an example of the structure obtained after cutting the leads in assembling the semiconductor device shown in FIG. 14; and FIG. 26 is a cross-sectional view showing an example of the structure obtained after the mounting onto a board in assembling the semiconductor device shown in FIG. 14.

[0091] The semiconductor device shown in FIGS. 14 to 16 is a semiconductor package of a resin-sealed type and a surface-mounting type employing a lead frame. In the description of a second embodiment, the semiconductor device 6 of a tab-embedded type is taken as an example of this semiconductor device.

[0092] As shown in FIG. 14, in the semiconductor device 6, a second surface of a first semiconductor chip 2, which is opposite to a first surface to be its circuit forming surface, is adhered and supported on a tab 1 e (chip mounting portion) via a conductive die bond material 8 a such as silver paste or adhering film. A second semiconductor chip 3 is stacked and mounted on the first surface via an insulative die bond material 8 b such as silicone rubber and insulative sheet, etc. Also, a plurality of electrode pads 2 a and 3 a of each semiconductor chip and a plurality of leads 1 a are connected by conductive wires 5 such as gold wires etc., respectively.

[0093] At this time, since the electrode pads in the periphery of the second semiconductor chip 3 are located inside those in the periphery of the first semiconductor chip 2, the plurality of electrode pads 2 a and 3 a of each semiconductor chip and a plurality of leads 1 a can be easily connected through the conductive wires 5.

[0094] Bumps made of gold etc. are formed on the electrode pads 3 a of the second semiconductor chip 3 in advance, for example, in the same manner as that used to form wire bumps. In the wire bonding, the side of each lead 1 a or the first semiconductor chip 2 is first bonded by using gold balls (tips) formed on the wires 5 (hereinafter “first bonding”). Thereafter, the tails (end) of the wires 5 are bonded to the bumps 3 b (hereinafter “second bonding”), whereby each angle of the wires 5 on the bumps 3 b becomes almost horizontal. Therefore, it is possible to keep lower the height of the wires and to achieve the reduction of thickness of the semiconductor device 6 even if the semiconductor chips are stacked.

[0095] The side of the first semiconductor chip 2 is connected by the first bonding, and the side of each lead 1 d is connected by the second bonding, and further the first semiconductor chip 2 and the tab suspension leads 1 g are also wire-bonded. Therefore, portions of the tab suspension leads 1 g are exposed from the bottom surface, and the tab 1 e is embedded in the sealing resin portion 4.

[0096] The resin used to form the sealing resin portion 4 is, for example, thermosetting epoxy resin etc.

[0097] Next, the manufacturing method for the semiconductor device 6 according to the second embodiment will be described.

[0098] Since the manufacturing method from the preparation of the lead frame 1 shown in FIG. 17 to the die bonding step shown in FIG. 20 is the same as that in the first embodiment, the description thereof will be omitted.

[0099] However, in the lead frame 1 mentioned here, the surfaces of the tabs 1 e are, as shown in FIG. 18, located about 0.1 to 0.3 mm higher than those of other lead frame surfaces.

[0100] Next, as shown in FIG. 21, through the conductive wires 5 such as gold wires etc., the plurality of electrode pads 2 a of the first semiconductor chip 2 are connected to the plurality of leads 1 a, the tab suspension leads 1 g shown in FIG. 15, or some of the electrode pads 3 a of the second semiconductor chip 3. Furthermore, the plurality of electrode pads 3 a of the second semiconductor chip 3 are connected to the plurality of lead frames 1 d. In this case, bumps made of gold etc. are formed on the electrode pads 3 a of the second semiconductor chip 3 in advance, for example, in the same manner as that used to form wire bumps. The wire bonding is used as the first bonding on the side of each lead 1 a or the first semiconductor chip 2 and as the second bonding on the side of each bump 3 b. The second bonding is performed to the bumps 3 b.

[0101] Subsequently, as shown in FIG. 22, the plurality of first semiconductor chips 2, the plurality of second semiconductor chips 3, the plurality of wires 5, and the leads 1 a and the tabs 1 e of the lead frame 1 are covered with a molding die 10, and the molding is performed by filling a sealing resin into a cavity 10 c of the molding die 10. In this manner, the resin sealing body 4 is formed as shown in FIG. 23.

[0102] The molding die 10 mentioned here has, as shown in FIG. 22, a shape such that cavities is partitioned per each of the plurality of device regions 1 k. This is different from that used in the package molding in the first embodiment.

[0103] Next, as shown in FIG. 23, a plating film 7 by solder is formed by, for example, an electroplating method on the surface of the external connection terminal 1 b of each lead 1 a exposed to the rear surface 4 a of the resin sealing body 4.

[0104] Subsequently, as shown in FIG. 24, the lead frame 1 is cut at regions other than the plurality of device regions 1 k by a cutting blade 13, thereby being divided into pieces as shown in FIG. 25.

[0105]FIG. 26 is an example showing a structure of a state where the semiconductor device 6 completed by the individualization is mounted onto the mounting board 11. Lands (uppermost layer wirings) 11 a are provided on one surface of the mounting board 11 so as to correspond to the leads 1 b and the tab suspension leads 1 g to be the external connection terminals of the semiconductor device 6. Thus, the leads 1 b and the tab suspension leads 1 g to be the external connection terminals of the semiconductor device 6 are overlapped on these lands lla, and are electrically connected via a connection material 12 such as solder etc.

[0106] The second embodiment has, in view of the reliability, a structure in which the tab rear surface exists inside the package. Also, in view of the heat radiation and the versatility for the size of the mounted chip, the tab is made smaller in size than the chip. Therefore, the region other than some portions of the leads 1 b and the tab suspension leads 1 g to be the external connection terminals of the semiconductor device 6 is covered with the sealing resin.

[0107] Consequently, as shown in FIG. 26, in the mounting board 11 on which the semiconductor device 6 is mounted, the uppermost layer wirings 11 a (wirings in the same layer as the mounting lands) can be formed also in the region below the region other than some of the leads 1 b and the tab suspension leads 1 g to be the external connection terminals, thereby allowing for achieving the improvement in a mounting capability.

[0108] Namely, in the case of the semiconductor device 6 described in the first embodiment, when the uppermost layer wiring lla (particularly, signal wiring) is arranged below the tab 1 e in the mounting board 11, the first semiconductor chip 2 is influenced by the noise from the wiring through the tab 1 e. Therefore, it is difficult to arrange the uppermost layer wiring 11 a of the mounting board 11 below the tab 1 e.

[0109] Thus, according to the semiconductor device 6 in the second embodiment, since the insulative sealing resin exists on the rear surface (mounting surface side) of the tab 1 e, it is possible to ensure the insulation on the rear surface of the tab 1 e and to reduce the influence due to the noise from the uppermost layer wiring 11 a of the mounting board 11. Therefore, as shown in FIG. 26, it is possible to arrange the uppermost layer wiring 11 a such as a signal wiring etc. on the mounting board 11 even just below the first semiconductor chip 2 and the tab 1 e.

[0110] As a result, it is possible to increase a wiring density in the wiring board 11 and to achieve the downsizing of the mounting board 11. In the mounting board 11 mentioned here, an inner wiring 11 b is formed and the inner wiring 11 b is connected to the uppermost layer wiring 11 a through the via hole wiring 11 c. Furthermore, the lead 1 a of the semiconductor device 6 is connected to the uppermost layer wiring lla through the solder 12. Additionally, the uppermost layer wiring 11 a is partially covered with a solder resist film 11 d.

[0111] (Third Embodiment)

[0112]FIG. 27 is a cross-sectional view showing an example of a structure of a semiconductor device according to a third embodiment of the present invention, and FIG. 28 is a plan view showing the structure of the semiconductor device 6 shown in FIG. 27.

[0113] The semiconductor device shown in FIGS. 27 and 28 is a semiconductor package of a resin-sealed type and a surface-mounting type employing a lead frame. In the description of a third embodiment, the semiconductor device 6 is taken as an example of this semiconductor device.

[0114] As shown in FIG. 27, in the semiconductor device 6, a first surface of the first semiconductor chip 2, which is a circuit forming surface, is supported on one surface of a frame-shaped tab 1 e (chip mounting portion) through, for example, silicone rubber or insulative sheet or the like. A second surface of the second semiconductor chip 3, which is opposite to a first surface thereof, is stacked and mounted on the first surface of the first semiconductor chip 2 through an insulative die bond material 8 b such as silicone rubber or insulative sheet or the like. Also, a plurality of electrode pads 2 a and 3 a of each semiconductor chip and a plurality of leads 1 a are connected through conductive wires 5 such as gold wires etc., respectively.

[0115] At this time, the second semiconductor ship 3 is arranged in the opening of the frame-shaped tab 1 e. Also, since the electrode pads of the first semiconductor chip 2 are located outside the frame-shaped tab 1 e, the plurality of electrode pads 2 a and 3 a of each semiconductor chip can be easily connected to the plurality of leads 1 a and the frame-shaped tab 1 e through the conductive wires 5, respectively.

[0116] Bumps made of gold etc. are formed on the electrode pads 3 a of the second semiconductor chip 3 in advance, for example, in the same manner as that used to form wire bumps. In the wire bonding, the side of each lead 1 a or the first semiconductor chip 2 is first bonded by using gold balls (tips) formed on the wires 5 (hereinafter “first bonding”). Thereafter, the tails (end) of the wires 5 are bonded to the bumps 3 b (hereinafter “second bonding”), whereby each angle of the wires 5 on the bumps 3 b becomes almost horizontal. Therefore, it is possible to keep lower the height of the wires and to achieve the reduction of thickness of the semiconductor device 6 even if the semiconductor chips are stacked.

[0117] The side of the first semiconductor chip 2 is connected by the first bonding, and the side of each lead 1 a is connected by the second bonding, and further the first semiconductor chip 2 and the tab suspension leads 1 g are also wire-bonded. Accordingly, portions of the tab suspension leads 1 g are exposed from the mounting surface, and the tab 1 e is embedded in the resin sealing body 4.

[0118] Note that, in the third embodiment, since the first semiconductor chip 2 is arranged on one surface of the frame-shaped tab 1 e and the second semiconductor chip 3 is arranged in the opening of the frame-shaped tab 1 e, the height after mounting the respective semiconductor chips is not influenced from the thickness of the tab 1 e, thereby allowing for achieving the reduction in the thickness of the semiconductor device 6.

[0119] Next, the manufacturing method for the semiconductor device 6 according to the third embodiment will be described.

[0120] Although the manufacturing method is basically similar to that in the second embodiment, both methods are different in the following points.

[0121] The lead frame used here is basically similar to that used in the second embodiment shown in FIG. 17, but is different in that the inside of the tab 1 e is hollowed out and formed into a frame shape as shown in FIG. 28.

[0122] (1) Further, in the die bonding step, to support the first semiconductor chip 2 on the one surface of the tab 1 e as shown in FIG. 27, for example, silicone rubber, insulative sheet or the like 8 b is adhered on the rear surface of the tab 1 e in advance, and the first semiconductor chip 2 and the tab 1 e are positioned and then adhered. (2) Next, the second semiconductor chip 3 is supported on the first surface, which is the circuit forming surface of the first semiconductor chip 2, through an insulative die bonding material 8 b such as insulative silicone rubber, insulative sheet or the like. Note that step (1) may be performed after step (2).

[0123] Subsequently, as shown in FIG. 27, through conductive wires 5 such as gold wires etc., the plurality of electrode pads 2 a of the first semiconductor chip 2 are connected to the plurality of leads 1 a, the tab 1 e, or some of the electrode pads 3 a of the second semiconductor chip 3. Furthermore, the plurality of electrode pads 3 a of the second semiconductor chip 3 are connected to the plurality of leads 1 a or the tab 1 e. In this case, bumps made of gold etc. are formed on the electrode pads 3 a of the second semiconductor chip 3 in advance, for example, in the same manner as that used to form wire bumps. The wire bonding is used as the first bonding on the side of each lead 1 a or the first semiconductor chip 2, and as the second bonding on the bump side. The second bonding is performed to the bumps.

[0124] The subsequent manufacturing method and mounting method from the molding step to the cutting step are identical to those in the second embodiment.

[0125] The semiconductor device shown in FIGS. 29 and 30 is a modified example of the semiconductor device in the third embodiment, in which the second surface of the second semiconductor chip 3 is exposed on the mounting surface 4 a of the semiconductor device 6. FIG. 29 is a cross-sectional view showing a modified example in the third embodiment. The plan view of FIG. 29 is equivalent to FIG. 28, and FIG. 30 is a bottom plan view (mounting surface) showing the structure of the semiconductor device shown in FIG. 29.

[0126] When the structure of this modified example is employed, it is possible to achieve the largest thickness reduction of the semiconductor device in comparison with other embodiments.

[0127] (Fourth Embodiment)

[0128]FIG. 31 is a cross-sectional view showing an example of a structure of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 32 is a plan view showing the structure of the semiconductor device 6 shown in FIG. 31.

[0129] The semiconductor device shown in FIGS. 31 to 33 is a semiconductor package of a resin-sealed type and a surface-mounting type employing a lead frame. In the description of a fourth embodiment, the semiconductor device 6 is taken as an example of this semiconductor device.

[0130] As shown in FIG. 31, in the semiconductor device 6, a first semiconductor chip 2 is supported on one surface of a tab 1 e through insulative silicone rubber, insulative sheet or the like 8 b, and a second semiconductor chip 3 is stacked and mounted on the other surface of the tab 1 e through a conductive die bonding material 8 a such as silver paste or adhering film. Also, a plurality of electrode pads 2 a and 3 a of each semiconductor chip and a plurality of leads 1 a are connected through conductive wires 5 such as gold wires etc., respectively.

[0131] At this time, since the second semiconductor chip 3 is located inside the tab 1 e and the electrode pads in the periphery of the first semiconductor chip 2 are located outside the tab 1 e, the plurality of electrodes of each semiconductor chip can be easily connected to the plurality of leads 1 a and the tab 1 e through the conductive wires 5.

[0132] The plurality of electrode pads 3 a of the second semiconductor chip 3 are connected to the plurality of leads 1 a or the tab 1 e. In this case, bumps made of gold or the like are formed on the electrode pads 3 a of the second semiconductor chip 3 in advance, for example, in the same manner as that used to form wire bumps. In the wire bonding, the side of each lead 1 a or the first semiconductor chip 2 is first bonded by using gold balls (tips) formed on the wires 5 (hereinafter “first bonding”). Thereafter, the tails (end) of the wires 5 are bonded to the bumps 3 b (hereinafter “second bonding”), whereby each angle of the wires 5 on the bumps 3 b becomes almost horizontal. Therefore, it is possible to keep lower the height of the wires and to achieve the reduction in thickness of the semiconductor device 6 even if the semiconductor chips are stacked.

[0133] The sides of the electrode pads 2 a are connected by the first bonding, and those of the leads 1 a are connected by the second bonding, and further the first semiconductor chip 2 and the tab suspension leads 1 g are also wire-bonded. Accordingly, portions of the tab suspension leads 1 g are exposed from the mounting surface and the first semiconductor chip 2 is embedded in the resin sealing body 4.

[0134] Next, the manufacturing method for the semiconductor device 6 according to the fourth embodiment will be described.

[0135] Although the manufacturing method is basically similar to that in the second embodiment, both methods are different in the following points.

[0136] (1) In the die bonding step, to support the first semiconductor chip 2 on the one surface of the tab 1 e as shown in FIG. 31, for example, silicone rubber, insulative thermosetting adhering sheet or the like is adhered on the one surface of the tab 1 e in advance, and the first semiconductor chip 2 and the tab 1 e are positioned and then adhered.

[0137] (2) Next, the second semiconductor chip 3 is supported on the other surface of the tab le through the insulative die bonding material 8 a such as silver paste or adhering film. Note that step (1) may be performed after step (2).

[0138] Subsequently, as shown in FIG. 31, the plurality of electrode pads 2 a of the first semiconductor chip 2 are connected to the plurality of lead frames 1 d, the tab 1 e, or some of the electrode pads 3 a of the second semiconductor chip 3 through the conductive wires 5 such as gold wires etc. Furthermore, the plurality of electrode pads 3 a of the second semiconductor chip 3 are connected to the plurality of leads 1 a or the tab 1 e. In this case, bumps made of gold etc. are formed on the electrode pads 3 a of the second semiconductor chip 3 in advance, for example, in the same manner as that used to form wire bumps. The wire bonding is used as the first bonding on the side of each lead 1 a or the first semiconductor chip 2, and as the second bonding on the bump side. The second bonding is performed to the bumps.

[0139] The subsequent manufacturing method and mounting method from the molding step to the cutting step are identical to those in the second embodiment.

[0140] The semiconductor device shown in FIG. 33 is a modified example of the semiconductor device in the fourth embodiment, in which the second surface of the second semiconductor chip 3 is exposed on the mounting surface 4 a of the semiconductor device 6. FIG. 33 is a cross-sectional view showing a modified example in the fourth embodiment. The plan view of FIG. 33 is equivalent to FIG. 32, and the bottom plan view (mounting surface) showing the structure of the semiconductor device in FIG. 33 is the same as FIG. 30.

[0141] Next, the modified example of wire bonding layout in the fourth embodiment of the present invention is shown in FIGS. 34 to 37. FIG. 34 is a plan view of a semiconductor device showing the case where a microcomputer is stacked on the first semiconductor chip 2 and an SRAM is stacked on the second semiconductor chip 3 in the semiconductor device; FIG. 35 shows an example of the semiconductor device in which external connection terminals are arranged on two sides and is a plan view of the semiconductor device showing the case where a flash microcomputer is stacked on the first semiconductor chip 2 and a DRAM is stacked on the second semiconductor chip 3; FIG. 36 is a plan view of the semiconductor device showing the case where a flash microcomputer is stacked on the first semiconductor chip 2 and a DRAM is stacked on the second semiconductor chip 3 in the semiconductor device; and FIG. 37 is plan view of the semiconductor device showing the case where a microcomputer is stacked on the first semiconductor chip 2 and two SRAMs are stacked on the second and third semiconductor chips in the semiconductor device.

[0142]FIGS. 38 and 39 show the state where the above-mentioned embodiment of the present invention is mounted on the multi-chip module; FIG. 38 is a cross-sectional view showing an example of its structure; and FIG. 39 is a plan view showing an example of its structure. The multi-chip module is mounted on the board together with a flip chip, thereby allowing for achieving the reductions in the size of the mounting area on the board and in the mounting height.

[0143] In the foregoing, the present invention has been concretely described based on the embodiments, but, needless to say, is not limited to the above-mentioned embodiments and can be variously modified and changed without departing from the gist thereof.

[0144] For example, in the above-described embodiments of the present invention, the example, in which the present invention is applied to the manufacture of the semiconductor device of which external connection terminals are arranged on the four sides, has been mainly described. However, the present invention may be applied to, for example, the manufacture of the semiconductor device of which external connection terminals are arranged on the two sides, thereby allowing for obtaining the same advantages.

[0145] By adopting a non-lead type package employing a lead frame in a multi-chip type package semiconductor device in which chips are stacked in and mounted on one package, it is possible to reduce the mounting height, the size of the mounting area, and the weigh thereof. Additionally, it is also possible to realize the semiconductor device at low cost since the existing apparatus is used. Also, since there are only a few restrictions for the chip size and for the arrangement of the electrode pads in stacking the LSI chips, the existing LSI chips can be used in combination: In addition, the tab or the electrode pads of the LSI chips can be used as connector terminals in the electrical connection between the two LSI chips stacked, thereby allowing for improving the versatility at the time of the extension of the leads. 

What is claimed is:
 1. A semiconductor device comprising: a sealing body made of an insulative resin; a tab on which a semiconductor chip is mounted; a plurality of leads each having one surface exposed on a mounting surface of said sealing body; a first semiconductor chip located in said sealing body and having a first surface to be a circuit forming surface and a second surface opposite to the first surface, the second surface being supported on one surface of said tab through adhesive; a plurality of electrode pads formed in the periphery of the first surface of said first semiconductor chip; conductive wires for electrically connecting said electrode pads and said leads; a second semiconductor chip having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and stacked and mounted on the first surface of the first semiconductor chip toward the second surface thereof; a plurality of electrode pads formed on the first surface of said second semiconductor chip; and conductive wires for electrically connecting the electrode pads of said second semiconductor chip and said leads.
 2. The semiconductor device according to claim 1, wherein said second semiconductor chip is arranged at a position inside the electrodes of said first semiconductor chip.
 3. The semiconductor device according to claim 1, wherein bumps are formed on the electrode pads of said second semiconductor chip, one end of each of said wires is connected to each of said leads or the electrode pads of said first semiconductor chip, and the other end thereof is connected through each of said bumps.
 4. The semiconductor device according to claim 1, wherein at least one of the plurality of electrode pads of said first semiconductor chip are electrically connected to said tab by said wires.
 5. The semiconductor device according to claim 1, wherein one surface of said tab is exposed on the mounting surface of said sealing body.
 6. The semiconductor device according to claim 1, wherein said tab is arranged at a position inside the periphery of said first semiconductor chip, and the second surface of said first semiconductor chip is closely adhered to said insulative resin at the position outside the periphery of said tab.
 7. A semiconductor device comprising: a sealing body made of an insulative resin; a tab for supporting a semiconductor chip; a plurality of leads each having one surface exposed on a mounting surface of said sealing body; a first semiconductor chip located in said sealing body, having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and supported on one surface of said tab through adhesive; a plurality of electrode pads formed in the periphery of the first surface of said first semiconductor chip; conductive wires for electrically connecting said electrode pads and said leads; a second semiconductor chip having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and stacked and mounted on the first surface of the first semiconductor chip; and conductive wires for electrically connecting a plurality of electrode pads formed on the first surface of said second semiconductor chip and said leads, wherein said tab is formed into a frame shape; the first semiconductor chip is adhered to one surface of the frame-shaped tab at a position inside the electrode pads on the first surface thereof; said second semiconductor chip is located on the first surface of said first semiconductor chip and at a position inside an opening of said frame-shaped tab; and said frame-shaped tab and said second semiconductor chip are adhered on the same surface.
 8. The semiconductor device according to claim 7, wherein said first semiconductor chip and said second semiconductor chip are connected to each other by connecting at least two of the electrode pads formed on each first surface through said conductive wires, or connected to said frame-shaped tab through said conductive wires.
 9. The semiconductor device according to claim 7, wherein the second surface of said first semiconductor chip is exposed to the mounting surface of said sealing body.
 10. The semiconductor device according to claim 7, wherein the second surface of said first semiconductor chip is sealed in said insulative resin.
 11. A semiconductor device comprising: a sealing body made of an insulative resin; a tab for supporting a semiconductor chip; a plurality of leads each having one surface exposed on a mounting surface of said sealing body; a first semiconductor chip located in said sealing body, having a first surface to be a circuit forming surface and a second surface opposite to the first surface, and supported on one surface of said tab through adhesive; a plurality of electrode pads formed in the periphery of the first surface of said first semiconductor chip; and conductive wires to electrically connect said electrode pads and said leads, wherein the device includes a second semiconductor chip having a first surface to be a circuit forming surface and a second surface opposite to the first surface; the second surface of said second semiconductor chip is adhered to one surface of said tab; said electrode pads and said leads and a plurality of electrode pads formed on the first surface of said second semiconductor chip are electrically connected through the conductive wires; the first surface of said first semiconductor chip is adhered to the other surface of said tab; and said tab and said second semiconductor chip are each located at a position inside the electrode pads on the first surface of the first semiconductor chip.
 12. The semiconductor device according to claim 11, wherein said first semiconductor chip and said second semiconductor chip are connected to each other by connecting at least two of the electrode pads formed on each first surface through said conductive wires, or connected to said tab through said conductive wires.
 13. The semiconductor device according to claim 11, wherein the second surface of said first semiconductor chip is exposed to the mounting surface of said sealing body.
 14. The semiconductor device according to claim 11, wherein the second surface of said first semiconductor chip is sealed in said insulative resin. 